The present invention relates generally to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with specialized channel regions.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed above a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking characteristic of the silicon dioxide spacers. The deep source and drain regions are necessary to provide sufficient material to connect contacts to the source and drain regions.
As transistors become smaller, it is desirous to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon germanium (Sixe2x80x94Ge) epitaxial layer above a glass (SiO2) substrate. The Sixe2x80x94Ge epitaxial layer can be formed by a technique in which a semiconductor thin film, such as, an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H) or the like is melted and crystallized by the irradiation of pulse laser beams.
In a bulk type device, such as, a metal oxide semiconductor field effect transistor (MOSFET), the use of Sixe2x80x94Ge materials could be used to increase charge carrier mobility, especially hole type carriers. A channel region containing germanium can have carrier mobility 2-5 times greater than a conventional Si channel region due to reduced carrier scattering and due to the reduced mass of holes in the germanium-containing material. According to conventional Sixe2x80x94Ge formation techniques for bulk-type devices, a dopant implanted molecular beam epitaxy (MBE) technique forms a Sixe2x80x94Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment and is not feasible for mass production of ICs.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility. Further still, there is a need for transistors with a thin Sixe2x80x94Ge channel region and deep source and drain regions. Even further still, there is a need for a method of manufacturing a transistor having a thin Sixe2x80x94Ge channel region on a bulk-type semiconductor substrate.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing an amorphous semiconductor material, annealing the amorphous semiconductor material, and doping to form source and drain regions. The amorphous semiconductor material contains germanium and is provided above a bulk substrate of semiconductor material. A single crystalline semiconductor layer containing germanium is formed from the amorphous semiconductor material via solid phase epitaxy. The source and drain regions can be formed by doping the single crystalline semiconductor layer and the substrate at a source location and a drain location. A channel region between the source region and the drain region includes a thin semiconductor germanium region.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a transistor. The method includes steps of depositing an amorphous silicon germanium material above a top surface of a semiconductor substrate, crystallizing the amorphous silicon germanium material utilizing solid phase epitaxy, depositing an amorphous silicon material above the crystallized silicon germanium material, crystallizing the amorphous silicon material utilizing solid phase epitaxy, and providing a source region and a drain region for the transistor. The source region and the drain region are deeper than a combined thickness of the silicon germanium material and the silicon material.
Still another embodiment relates to a process of forming a transistor with a silicon germanium channel region. The process includes depositing a thin amorphous silicon germanium material, crystallizing the amorphous silicon germanium material via solid phase epitaxy, depositing a thin amorphous silicon material, crystallizing the amorphous silicon material via solid phase epitaxy, and providing a source region and a drain region for the transistor. The thin amorphous silicon germanium material is provided above a top surface of a semiconductor substrate.